The escalating requirements for high-denisity and performance associated with ultra large-scale integration semiconductor wiring require responsive changes in interconnection technology. Such escalating requirements have been found difficult to satisfy in terms of providing a low RC (resistance capacitance) interconnection pattern, particularly where sub-micron via contacts and trenches have high aspect ratios imposed by miniaturization.
Conventional semiconductor devices typically comprise a semiconductor substrate, normally of doped monocrystalline silicon, and a plurality of sequentially formed dielectric layer and conductive patterns. An integrated circuit is formed containing a plurality of conductive patterns, and a plurality of interconnect lines, such as bus lines, bit-lines, and logic interconnect lines. Typically, the conductive patterns on different layers, i.e., upper and lower layers, are electrically connected by a conductive plug filling a via hole, while a conductive plug filling a contact hole establishes electrical contact with an active region on a semiconductor substrate, such as a source/drain region. Conductive lines are formed on a substrate layer or in trenches and typically extend substantially horizontal with respect to the semiconductor substrate. Semiconductor "chips" comprising five or more levels of metallization are becoming more prevalent as device geometries shrink to sub-micron levels.
A conductive plug filling a via hole is typically formed by depositing a dielectric interlayer on a conductive layer comprising at least one conductive pattern, forming an opening in the dielectric layer by conventional photolithographic and etching techniques, and filling the opening with a conductive material, such as tungsten (W). Excess conductive material on the surface of the dielectric layer is typically removed by chemical mechanical polishing (CMP). One such method is known as damascene and basically involves forming an opening in the dielectric interlayer and filling the opening with a metal. Dual damascene techniques involve forming an opening comprising a lower contact or a via hole section in communication with an upper trench section, which opening is filled with a conductive material, typically a metal, to simultaneously form a conductive plug and electrical contact with a conductive line.
High performance microprocessor applications require rapid speed of semiconductor circuitry. The control speed of semiconductor circuitry varies inversely with the resistance and capacitance of the interconnect pattern. As integrated circuits become more complex and feature sizes and spacings become smaller, the integrated circuit speed becomes less dependent upon the transistor itself and more dependent upon the interconnection pattern. Miniaturization demands long interconnects having small contacts and small cross-sections. Thus, the interconnection pattern limits the speed of the integrated circuit. If the interconnection node is routed over a considerable distance, e.g., hundreds of microns or more as in sub-micron technologies, the interconnection capacitance limits the circuit node capacitance loading, and, hence, the circuit speed. As integration density increases and feature size decreases in accordance with deep sub-micron design rules, e.g., a design rule of about 0.18 .mu.m and below, the rejection rate due to integrated circuit speed delays severely limits production throughput and significantly increases manufacturing costs.
In prior technologies, aluminum was used in very large scale integration interconnect metallization. Copper and copper alloys have received considerable attention as a candidate for replacing aluminum in these metallizations. Copper has a lower resistivity than aluminum and improved electrical properties vis-a-vis tungsten, making copper a desirable metal for use as a conductive plug as well as conductive wiring.
In the planarization of a copper containing conductive layer to stop on a barrier layer, wide conductive lines tend to "dish" and dense patterns tend to erode. This causes unwanted copper line thinning which increases resistance in the interconnections. The dishing and pattern erosion is caused by the high pressure and speed process conditions conventionally used to planarize ("polish") copper. Relatively high pressure and high speed process conditions are employed to provide a desirable copper removal rate and a uniform removal of the conductive layer. This single phase polishing produces a structure, such as depicted in prior art FIG. 4, exhibiting dishing and pattern erosion.
In order to avoid dishing and pattern erosion, a slower polishing and lower pressure process could be employed, but this would undesirably reduce the throughput and may have an effect on the uniformity of removal of the copper conductive layer. Furthermore, a greater amount of overpolishing is required by poor removal uniformity in order to complete the planarization process.
An approach to minimize dishing is described in U.S. Pat. No. 5,618,381 that employs a multiple step method of chemical-mechanical polishing. In the described method, a protective layer of material, such as silicon dioxide, borophosphosilicate glass, silicon nitride or tetraorthosilicate is formed over the metal surface of the layer of conductive material to be planarized. The protective layer is not as easily polished as the metal in a CMP process of the protective layer from the underlying metal overburden. A second CMP process, which removes the metal at a greater rate than the protective layer, is said to prevent the polishing pad from dishing metal in the areas having larger metal features such as large metal buses and bond pads.
One of the significant disadvantages of the above approach is the additional steps taken to avoid the dishing effect. This includes the additional deposition steps employed to produce the protective layer of material on the metal. Also, it is possible for some of this material to remain on the wafer, possibly increasing the overall capacitance of the chip. The additional processing steps also have an adverse impact on wafer throughput.
There is a need for a method of planarizing a plated copper surface to remove most of the copper from the wafer surface using process conditions that produce a rapid, uniform removal of the copper for purposes for high throughput, while minimizing overpolishing necessitated by poor removal uniformity. The process needs to reduce the dishing and erosion that arises in conventional high speed and high pressure process conditions, while still maintaining acceptable throughput and uniformity.